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RT8260A 1 ds8260a-03 march 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. 1.8a, 24v, 1.4mhz step-down converter general description the RT8260A is a high voltage buck converter that can support the input voltage range from 4.5v to 24v and the output current can be up to 1.8a. current mode operation provides fast transient response and eases loop stabilization. the chip also provides protection functions such as cycle- by-cycle current limiting and thermal shutdown protection. the RT8260A is available in a wdfn-8l 2x2 package. features z z z z z wide operating input voltage range : 4.5v to 24v z z z z z adjustable output voltage range : 0.8v to 15v z z z z z 1.8a output current z z z z z 0.3 internal power mosfet switch z z z z z high efficiency up to 92% z z z z z 1.4mhz fixed switching frequency z z z z z stable with low esr output ceramic capacitors z z z z z thermal shutdown z z z z z cycle-by-cycle over current protection z z z z z rohs compliant and halogen free applications z distributed power systems z battery charger z pre-regulator for linear regulators z wled drivers typical application circuit pin configurations (top view) wdfn-8l 2x2 marking information jg : product code w : date code nc en sw nc boot gnd fb vin 7 6 5 1 2 3 4 8 gnd 9 vin en gnd boot fb sw 4 6, 9 (exposed pad) 5 3 2 7 l1 4.7h c boot 10nf c out 22f r1 62k r2 19.6k v out 3.3v c in 10f chip enable v in 4.5v to 24v RT8260A d1 b230a open = automatic startup jgw RT8260A package type qw : wdfn-8l 2x2 (w-type) lead plating system g : green (halogen free and pb free)
RT8260A 2 ds8260a-03 march 2011 www.richtek.com function block diagram functional pin description pin no. pin name pin function 1, 8 nc no internal connection. 2 sw switch output. 3 vin supply voltage. bypass vin to gnd with a suitable large capacitor to prevent large voltage spikes from appearing at the input. 4 en chip enable (active high). if the en pin is open, it will be pulled to high by internal circuit. 5 fb feedback. an external resistor divider from the output to gnd tapped to the fb pin sets the output voltage. the value of the divider resistors also set loop bandwidth. 6, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 7 boot bootstrap. a capacitor is connected between sw and boot pins to form a floating supply across the power switch driver. this capacitor is needed to drive the power switch?s gate above the supply voltage. v out (v) 1.2 1.8 2.5 3.3 5 8 10 15 l1 ( h) 2 2 3.6 4.7 6.8 10 10 15 r2 (k ) 124 49.9 29.4 19.6 13 8.2 6.49 4.2 r1 (k ) 62 62 62 62 68 75 75 75 c out ( f) 22 22 22 22 22 22 22 22 table 1. recommended component selection driver r q s bootstrap control + - ramp generator oscillator 1.4mhz + - pwm comparator ea reference regulator + - 1.1v 1a + - 400k 30pf 1pf shutdown comparator oc limit clamp current sense amp x20 boot gnd fb en vin sw 10k 3v 25m
RT8260A 3 ds8260a-03 march 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max unit feedback reference voltage v fb 4.5v v in 24v 0.79 0.8 0.81 v feedback current i fb v fb = 0.8v -- 0.1 0.3 a switch on resistance r ds(on) -- 0.3 -- switch leakage v en = 0v, v sw = 0v -- -- 10 a current limit i li m v boot ? v sw = 4.8v 2.2 2.9 -- a oscillator frequency f sw 1.2 1.4 1.6 mhz maximum duty cycle -- 75 -- % minimum on-time t on -- 100 -- ns under voltage lockout threshold rising 3.9 4.2 4.5 v under voltage lockout threshold hysteresis -- 200 -- mv en input low voltage -- -- 0.4 v en input high voltage 1.4 -- -- v en pull up current v en = 0v -- 1 -- a shutdown current i shdn v en = 0v -- 25 -- a quiescent current i q v en = 2v, v fb = 1v (not switching) -- 0.55 1 ma thermal shutdown t sd -- 150 -- c (v in = 12v, t a = 25 c unless otherwise specified) absolute maximum ratings (note 1) z supply voltage, v in ----------------------------------------------------------------------------------------- 26v z sw voltage --------------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z boot v oltage ------------------------------------------------------------------------------------------------ (v sw ? 0.3v) to (v sw + 6v) z all other pins ------------------------------------------------------------------------------------------------- 0.3v to 6v z power dissipation, p d @ t a = 25 c wdfn-8l 2x2 ------------------------------------------------------------------------------------------------- 0.833w z package thermal resistance (note 2) wdfn-8l 2x2, ja ------------------------------------------------------------------------------------------- 120 c/w wdfn-8l 2x2, jc ------------------------------------------------------------------------------------------- 8.2 c/w z junction temperature ------ --------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ----------------------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) --------------------------------------------------------------------------------- 2kv mm (machine mode) ---------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z supply voltage, v in ----------------------------------------------------------------------------------------- 4.5v to 24v z output voltage, v out --------------------------------------------------------------------------------------- 0.8v to 15v z en voltage, v en ---------------------------------------------------------------------------------------------- 0v to 5.5v z junction temperature range ------------------------------------------------------------------------------ ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------ ? 40 c to 85 c
RT8260A 4 ds8260a-03 march 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8260A 5 ds8260a-03 march 2011 www.richtek.com typical operating characteristics efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 0.3 0.6 0.9 1.2 1.5 1.8 load current (a) efficiency (%) v in = 12v v in = 24v v out = 5v output voltage vs. load current 3.306 3.311 3.316 3.321 3.326 3.331 3.336 0 0.3 0.6 0.9 1.2 1.5 1.8 load current (a) output voltage (v) v in = 12v current limit vs. temperature 2.0 2.3 2.6 2.9 3.2 3.5 3.8 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 12v, v out = 3.3v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 0.3 0.6 0.9 1.2 1.5 1.8 load current (a) efficiency (%) v in = 12v v in = 24v v out = 3.3v reference voltage vs. temperature 0.785 0.790 0.795 0.800 0.805 0.810 0.815 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = 12v, i out = 0a current limit vs. duty cycle 2.0 2.3 2.6 2.9 3.2 3.5 3.8 0 1632486480 duty cycle (%) peak current (a )
RT8260A 6 ds8260a-03 march 2011 www.richtek.com load transient response time (100 s/div) i out (1a/div) v out (100mv/div) v in = 12v, v out = 3.3v, i out = 0a to 1.8a time (250ns/div) output ripple v sw (5v/div) i l1 (1a/div) v in = 12v, v out = 3.3v, i out = 1.8a v out (10mv/div) output ripple time (250ns/div) v sw (10v/div) i l1 (1a/div) v in = 24v, v out = 3.3v, i out = 1.8a v out (10mv/div) load transient response time (100 s/div) i out (1a/div) v out (100mv/div) v in = 12v, v out = 3.3v, i out = 0.9a to 1.8a switching frequency vs. temperature 1.20 1.25 1.30 1.35 1.40 1.45 1.50 -50-25 0 25 50 75100125 temperature (c) switching frequency (mhz) 1 v in = 12v, i out = 0.3a quiescent current vs. temperature 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -50 -25 0 25 50 75 100 125 temperature (c) quiescent current (ma ) v in = 12v, v en = 2v, v fb = 1v
RT8260A 7 ds8260a-03 march 2011 www.richtek.com power on from en time (250 s/div) v out (2v/div) i l1 (2a/div) v in = 12v, v out = 3.3v, i out = 1.8a v en (2v/div) power off from en time (50 s/div) v out (2v/div) i l1 (2a/div) v in = 12v, v out = 3.3v, i out = 1.8a v en (2v/div)
RT8260A 8 ds8260a-03 march 2011 www.richtek.com application information the RT8260A is a high voltage buck converter that can support the input voltage range from 4.5v to 24v and the output current can be up to 1.8a. output voltage setting the resistive voltage divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. figure 1. output voltage setting for adjustable voltage mode, the output voltage is set by an external resistive voltage divider according to the following equation : ?? + ?? ?? out fb r1 v = v1 r2 figure 2. external bootstrap diode out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the value of i l = 0.24 (i max = 1.8) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. diode selection when the power switch turns off, the path for the current is through the diode connected between the switch output and ground. this forward biased diode must have a minimum voltage drop and recovery times. schottky diode is recommended and it should be able to handle those current. the reverse voltage rating of the diode should be greater than the maximum input voltage, and current rating should be greater than the maximum load current. for more detail, please refer to table 3. where v fb is the feedback reference voltage (0.8v typ.). external bootstrap diode connect a 10nf low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and the boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65%. the bootstrap diode can be a low cost one such as 1n4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the RT8260A. note that the external boot voltage must be lower than 5.5v. RT8260A gnd fb r1 r2 v out sw boot 5v RT8260A 10nf table 2. suggested inductors for typical application circuit component supplier series dimensions (mm) tdk vlc6045 6 x 6 x 4.5 tdk slf12565 12.5 x 12.5 x 6.5 taiyo yuden nr8040 8 x 8 x 4 the inductor's current rating (defined by that which causes a temperature rise from 25 c ambient to 40 c ) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. refer to table 2 for the suggested inductor selection.
RT8260A 9 ds8260a-03 march 2011 www.richtek.com c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : out in rms out(max) in out v v i = i 1 vv ? this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the required effective series resistance (esr) to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. component supplier series v rrm (v) i out (a) package diodes b220a 20 2 sma diodes b230a 30 2 sma panjit sk22 20 2 do- 214aa panjit sk23 30 2 do- 214aa table 3. suggested diode aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr) also begins to charge or discharge c out generating a feedback error signal for the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. emi consideration since parasitic inductance and capacitance effects in pcb circuitry would cause a spike voltage on the sw pin when the high side mosfet is turned-on/off, this spike voltage on sw may impact emi performance in the system. in order to enhance emi performance, there are two methods to suppress the spike voltage. one is to place an r-c snubber between sw and gnd and place them as close as possible to the sw pin (see figure 3). another method is to add a resistor in series with the bootstrap capacitor, c boot . but this method will decrease the driving capability to the high side mosfet. it is strongly recommended to
RT8260A 10 ds8260a-03 march 2011 www.richtek.com layout consideration follow the pcb layout guidelines for optimal performance of RT8260A. ` keep the traces of the main current paths as short and wide as possible. ` place the input capacitor as close as possible to the device pins (vin and gnd). ` sw node is with high frequency voltage swing and should be kept in a small area. keep sensitive components away from the sw node to prevent stray capacitive noise pick-up. ` place the feedback components as close to the fb pin as possible. ` connect gnd to a ground plane for noise reduction and thermal dissipation. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula: p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8260A, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn- 8l 2x2 packages, the thermal resistance, ja , is 120 c / w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (120 c /w) = 0.833w for wdfn-8l 2x2 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8260A package, the derating curve in figure 4 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 4. derating curves for RT8260A packages reserve the r-c snubber during pcb layout for emi improvement. moreover, reducing the sw trace area and keeping the main power in a small loop will be helpful for emi performance. for detailed pcb layout guide, please refer to the section on layout consideration. figure 3. reference circuit with snubber and enable timing control 4.5v to 24v vin en boot fb sw 4 5 3 2 7 l 4.7h 10nf 22f r1 49.9k r2 16k v out 3.3v/1.8a 10f chip enable v in RT8260A c boot c out c in r en * c en * r boot * r s * c s * * : optional b230a gnd 6, 9 (exposed pad) 0.00 0.15 0.30 0.45 0.60 0.75 0.90 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8260A 11 ds8260a-03 march 2011 www.richtek.com figure 5. pcb layout guide table 4. suggested capacitors for cin and cout location component supplier part no. capacitance ( m f) case size c in murata grm31cr61e106k 10 1206 c in tdk c3225x5r1e106k 10 1206 c in taiyo yuden tmk316bj106ml 10 1206 c out murata grm31cr61c226m 22 1206 c out tdk c3225x5r1c226m 22 1206 c out taiyo yuden emk316bj226ml 22 1206 nc sw nc boot gnd vin en 7 6 5 1 2 3 4 8 g n d 9 fb sw v o u t gnd c in the input capacitor must be placed as close to the ic as possible. the feedback components must be connected as close to the device as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. r1 r2 v out r s c s c out d l vin gnd
RT8260A 12 ds8260a-03 march 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension w-type 8l dfn 2x2 package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.950 2.050 0.077 0.081 d2 1.000 1.250 0.039 0.049 e 1.950 2.050 0.077 0.081 e2 0.400 0.650 0.016 0.026 e 0.500 0.020 l 0.300 0.400 0.012 0.016 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. detail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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